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LOW-POWER SRAM MEMORY CELL AND APPLICATION STRUCTURE THEREOF

发布者:技术转移办公室发布时间:2021-10-15浏览次数:10

技术主题:后摩尔器件与集成系统

发明名称:LOW-POWER SRAM MEMORY CELL AND APPLICATION STRUCTURE THEREOF

申请时间:2020-06-17

申请号:US17051783

摘要:A low-power SRAM memory cell includes five word lines and four bit lines. The five word lines are a first word line, a second word line, a third word line, a fourth word line and a fifth word line. The four bit lines are a first bit line, a second bit line, a third bit line, and a fourth bit line. During the operation process of calculating a binary 10×11, the first word line is 1, the second word line is 0, the third word line is 0, the fourth word line is 1, the high bit stored in the bit cell is 1, and the low bit is 1. The voltage value of the fifth word line is 0.73 volt. At this time, the first bit line, the second bit line, and the third bit line do not discharge, while the fourth bit line discharges.

技术转移办公室简介

跨界引领创新创业生态,营造创新创业氛围,运营自主知识产权,孵

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产业和经济的影响力,践行学校使命,做出时代贡献。


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